During the fabrication of modern silicon (Si)-based metal oxide semiconductor field effect transistors (MOSFETs), a number of thermal processes are required to be performed. One of the highest thermal budget steps employed in a MOSFET fabrication sequence is that required to electrically activate the polycrystalline silicon (e.g., poly-Si) gate electrode, which has been the industry standard material. For example, a temperature on the order of about 900° C. or greater is typically employed to electrically activate prior art poly-Si gate electrodes.
As other materials are being considered for use in high-performance MOSFET devices, such as, for example, a germanium (Ge)-channel region, high temperature processing steps can no longer be tolerated. In the case of Ge, for example, the Ge will melt at a temperature of about 940° C. Also, the material for the gate electrode must be compatible (i.e., non-contaminating) with the various cleaning and processing tools used to fabricate MOSFET devices.
The use of polycrystalline germanium (e.g., poly-Ge) as a gate electrode material has been disclosed in U.S. Pat. No. 5,250,452 by Ozturk et al. as a feasible low-temperature replacement material for poly-Si gates. In accordance with the disclosure of the '452 patent, a method is provided in which a layer of polycrystalline silicon is deposited on a silicon dioxide layer to a thickness which is thick enough to support the subsequent deposition of germanium thereon.
The problem with the approach disclosed in the '452 patent is twofold. First, and as stated above, the '452 patent requires that a poly-Si layer be formed directly atop the silicon dioxide gate dielectric in order to be capable of growing a Ge layer. This is required in the '452 patent since poly-Ge does not effectively grow on silicon dioxide as does poly-Si. One of the major concerns in modern integrated circuit (IC) manufacturing is to minimize the gate-depletion effects in which the reduced conductivity of the lower portion of the gate electrode acts as a parasitic capacitance. The poly-Si layer employed in the '452 patent described above would exacerbate this problem even further than it exists currently because the poly-Si layer would never be properly activated by the low-temperature process proposed.
The second issue with using a poly-Ge gate material is due to the significantly increased chemical reactivity (as compared to poly-Si) with most standard Si-based processes including, for example, both wet and dry etching processes. Because of this enhanced reactivity, degradation of the poly-Ge gate material may occur during the various IC fabrication steps.
In view of the above, there is needed a method of fabricating a metal oxide semiconductor (MOS) gate electrode that is electrically activated at low processing temperatures. By “low processing temperatures” it is meant a temperature that is less than 750° C. A method of fabricating a MOS gate electrode is also needed that minimizes gate-depletion effects, does not contaminate a standard MOS fabrication facility and has sufficiently low reactivity of the exposed surfaces that renders such a MOS gate electrode compatible with conventional MOSFET processing steps.